1. Field of the Invention
This invention relates to manufacture of semiconductor devices and more particularly to end point detection in manufacture thereof.
2. Description of Related Art
U.S. Pat. No. 4,646,425 of Owens for "Method for Making a Self-Aligned CMOS EPROM wherein the EPROM Floating Gate and CMOS Gates Are Made from One Polysilicon Layer" describes a method of forming Floating EPROM and CMOS gates from a single polysilicon layer. A CMOS EPROM is made wherein the typical EPROM device is an N-channel IGFET Insulated Gate Field Effect Transistor) with its control gate self-aligned with its floating gate. The EPROM floating gate and the gates of both the P-channel and N-channel peripheral circuit transistors are formed from a first polysilicon layer and the control gate is formed from a later deposited polysilicon layer.
Owens states as follows: "Erasable programmable read only memories are well known in the semiconductor art. EPROM circuits include a matrix of EPROM devices, each of which stores a bit of information, and a plurality of peripheral transistor devices. Peripheral transistors are required for such functions as row decode and column decode of the EPROM matrix, latches and drivers."
"In addition to having a control gate similar to the control gate of the peripheral devices, EPROM devices have a floating gate positioned below the control gate. It is this floating gate which allows the EPROM device to store charge, thereby programming the EPROM device. Conversely, when the EPROM device is unprogrammed, the floating gate is uncharged."
"The architecture required places constraints on the size of the EPROM device. Since the floating gate must rest directly below the control gate, both gates must be large enough to allow their proper alignment. Self-alignment of both the control gate and the floating gate allows a reduction in the size of the EPROM device."
U.S. Pat. No. 5,286,667 of Lin et al. for "Modified and Robust Self-Aligning" shows a method of forming self-aligning contacts. A silicon nitride or silicon oxynitride barrier layer is used as an end point detection layer for the plasma etch. A method is described for making an IC device having a combination of a capacitor and MOSFET transistor with gate electrodes and source/drain regions using silicon nitride or silicon oxynitride barrier layers as a key to an LDD spacer etch process. The barrier layer aids in endpoint detection for the plasma etch. This allows for less loss of the field oxide and greater thickness control of the field oxide regions. Further, the silicon nitride endpoint detection allows for the removal of undesirable residual silicon oxide from the surface of the capacitor plate without loss of the polysilicon capacitor plate itself.
U.S. Pat. No. 4,829,024 of Klein et al. for "Method of Forming Layered Polysilicon Filled Contact by Doping Sensitive End Point Etching" describes a semiconductor process for forming a very low resistance contact. A straight wall contact is formed conventionally above a silicon substrate. Then a blanket metal barrier layer is deposited. Several planar polysilicon layers are deposited above the metal barrier layer. The polysilicon layers have varying doping levels and then the process of etched away those layers begins. By monitoring a by-product gas of the etch reaction the transition between polysilicon layers is monitored. In the contact region, a layer of doped polysilicon is left above the metal barrier. Metal may then be patterned over the entire structure to provide a low resistance reliable contact.
U.S. Pat. No. 5,091,327 of Bergemont for "Fabrication of a High Density Stacked Gate EPROM Split Cell with Bit Line Reach-Through and Interruption Immunity" describes a method for fabricating a split-gate EPROM cell utilizing stacked etch techniques. A layer of silicon dioxide is formed on a P-silicon substrate. A layer of polysilicon is formed on the silicon dioxide layer, followed by growth of an oxide/silicon nitride/oxide (ONO) layer. The ONO and polysilicon layers are etched to define floating gates. Next, an edge of each floating gate is utilized in a self-aligned implant of buried N+ bit lines. The floating gate extends only over a first portion of the channel defined between the adjacent buried bit lines. A differential oxide layer is grown on the substrate between adjacent floating gates in a low temperature steam oxidation step so the oxide formed over the exposed portion of the buried N+ bit line is thicker than the oxide formed over the exposed portion of the channel. Following formation of the differential oxide layer, a second layer of polysilicon is formed and etched to define control lines extending perpendicular to the floating gates in the conventional split-gate EPROM cell structure. The control gates are utilized in a stacked etch to complete the split-gate cells. The etch is carried out such that the oxide overlying the N+ bit lines protect the surface of the substrate, avoiding bit line interruption, while the silicon dioxide overlying the exposed portion of the channel is overetched to form a trench into the channel that extends below the junction depth of the N+ region, thereby eliminating bit line to bit line reach-through.
In some conventional cases, etching by the Reactive Ion Etching (RIE) process requires enough etching area to detect the End Point (E/P) signal, especially for embedded memory self-aligned etching, buried contact, emitter contact, etc. However, when there is less exposed area occupying a small portion of a chip, the result is the failure of end point detection as the etching process is performed. Although this problem can be solved by changing from the use of the end point (E/P) detection mode to the use of the time mode, the degree of overetching (O/E) and the Si-trench depth of Si in the chip will be uncontrollable, to a seriously degree, due to fluctuations of the E/R etching process.